Anant joined ALGO in Oct 2010 to work on implementation of power efficient signaling methods for chip to chip communication.
Prior to joining ALGO, Anant was a Product Design Manager at Innovative Silicon's R&D offices at Lausanne where he led the development of micro-architecture and design of Z-RAM IP (1T cell, floating body) based memory solutions for L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products.
Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon as a senior member of the technical staff on several generations of Pentium and Core-duo processors.
Anant received his M.S.E.E. degree from University of Washington, Seattle in 1998.
Anant is now a lead engineer at Kandou Bus.