/* This is the template for an ALGO member's page */

/* 
    The image that goes into the square on the right.
    See bottom of http://algo.epfl.ch/en/private/howto
    for how-to create the image.
    Once ready, you can upload the image with the standard button (the forth from the right up here)
    Note the white space preceding the image address. This because the image has to be right-aligned
    in order to be placed in the correct place.
*/
{{  :en:group:members:rimg_anant.jpg|Portrait of Giovanni}}

/* Here you should write the content of the page (and remove the lorem ipsum placeholder */

Anant joined ALGO in Oct 2010 to work on implementation of power efficient signaling methods for chip to chip communication. 

Prior to joining ALGO, Anant was a Product Design Manager at [[http://www.z-ram.com|Innovative Silicon's]] R&D offices at Lausanne where he led the development of micro-architecture and design of Z-RAM IP (1T cell, floating body) based memory solutions for L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products. 

Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon as a senior member of the technical staff on several generations of Pentium and Core-duo processors.

Anant received his M.S.E.E. degree from University of Washington, Seattle in 1998.

Anant is now a lead engineer at [[http://www.kandou.com|Kandou Bus]].

/* 
  This is the database entry used to auto-generate some other page (e.g. the members listing page).
  - the dates should be in the form YYYY-MM-DD;
  - listgroup is used for sorting in the members listing page (a_amin for amin, b_NAME for natascha and invited profs, c_NAME for post-docs, d_NAME for phD students, e_NAME for developers
  - status can be active or past
  - table must be "members" 
*/
---- dataentry member ----
title :
fullname              : Anant Singh
link_title           : en:group:members:singh|Anant Singh
birthday_dt      :
join_dt             : 2010-10-01
left_dt              : 2011-02-31           
webpage_url    :  https://ch.linkedin.com/in/anant-singh-79a18310|Anant Singh
portrait_media     : en:group:members:rimg_anant.jpg
avatar_img64 : en:group:members:rimg_anant.jpg
email_mail       : anant.singh@epfl.ch     
tel                      : +41 21 693 13 43
position            : Engineer
listgroup           : e_asingh
state                : past
table              : members
Summary : Anant joined ALGO in Oct 2010 to work on implementation of power efficient signaling methods for chip to chip communication. Prior to joining ALGO, Anant was a Product Design Manager at [[http://www.z-ram.com|Innovative Silicon's]] R&D offices at Lausanne where he led the development of micro-architecture and design of Z-RAM IP (1T cell, floating body) based memory solutions for L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products. Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon as a senior member of the technical staff on several generations of Pentium and Core-duo processors.Anant received his M.S.E.E. degree from University of Washington, Seattle in 1998.He is now VP of Engineering at [[http://www.kandou.com|Kandou Bus]].
----