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| - | Anant joined ALGO in Oct 2010 to work on Kandou project which is funded by a grant from the MICS Spin Fund. | + | Anant joined ALGO in Oct 2010 to work on implementation of power efficient signaling methods for chip to chip communication. |
| - | Prior to joining ALGO, Anant was a Product Design Manager at Innovative Silicon's Swiss R&D offices at Lausanne where he led the development of micro-architecture and designs of Z-RAM IP (1T cell, floating body) based memory solutions for the L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products. | + | Prior to joining ALGO, Anant was a Product Design Manager at [[http://www.z-ram.com|Innovative Silicon's]] R&D offices at Lausanne where he led the development of micro-architecture and design of Z-RAM IP (1T cell, floating body) based memory solutions for L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products. |
| - | Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon where he was a senior member of the technical staff and contributed to several generations of Pentium and Core-duo processors. He was a key contributor for productization of a new logic family (LVS, low voltage swing) that enabled a dual pumped Integer Execution core on Pentium-4 processor to operate in excess of 8GHz. | + | Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon as a senior member of the technical staff on several generations of Pentium and Core-duo processors. |
| + | Anant received his M.S.E.E. degree from University of Washington, Seattle in 1998. | ||
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| + | Anant is now a lead engineer at [[http://www.kandou.com|Kandou Bus]]. | ||
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| birthday_dt : | birthday_dt : | ||
| join_dt : 2010-10-01 | join_dt : 2010-10-01 | ||
| - | left_dt : 2035-12-31 | + | left_dt : 2011-02-31 |
| - | webpage_url : | + | webpage_url : https://ch.linkedin.com/in/anant-singh-79a18310|Anant Singh |
| portrait_media : en:group:members:rimg_anant.jpg | portrait_media : en:group:members:rimg_anant.jpg | ||
| avatar_img64 : en:group:members:rimg_anant.jpg | avatar_img64 : en:group:members:rimg_anant.jpg | ||
| email_mail : anant.singh@epfl.ch | email_mail : anant.singh@epfl.ch | ||
| tel : +41 21 693 13 43 | tel : +41 21 693 13 43 | ||
| - | position : Collaborateur Scientifique | + | position : Engineer |
| - | listgroup : c_asingh | + | listgroup : e_asingh |
| - | status : active | + | state : past |
| table : members | table : members | ||
| + | Summary : Anant joined ALGO in Oct 2010 to work on implementation of power efficient signaling methods for chip to chip communication. Prior to joining ALGO, Anant was a Product Design Manager at [[http://www.z-ram.com|Innovative Silicon's]] R&D offices at Lausanne where he led the development of micro-architecture and design of Z-RAM IP (1T cell, floating body) based memory solutions for L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products. Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon as a senior member of the technical staff on several generations of Pentium and Core-duo processors.Anant received his M.S.E.E. degree from University of Washington, Seattle in 1998.He is now VP of Engineering at [[http://www.kandou.com|Kandou Bus]]. | ||
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