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Anant joined ALGO in Oct 2010 to work on implementation of power efficient signaling methods for chip to chip communication.

Prior to joining ALGO, Anant was a Product Design Manager at Innovative Silicon's R&D offices at Lausanne where he led the development of micro-architecture and design of Z-RAM IP (1T cell, floating body) based memory solutions for L3 cache in AMD's lead microprocessors and Hynix's DDR3 based DRAM products.

Anant worked at Intel Corp from 1999 to 2005 in Portland, Oregon as a senior member of the technical staff on several generations of Pentium and Core-duo processors. He was a key contributor for the productization of a novel logic family (LVS, low voltage swing) that enabled a dual pumped Integer Execution core and L0 cache on Pentium-4 processor to operate in excess of 8GHz. This work was published in IEEE's Journal of Solid State Circuits in 2005.

Anant received his M.S.E.E. degree from University of Washington, Seattle in 1998.