Title

One of the major issues in design of ultra-low power (ULP) integrated systems is the wasted power due to the leakage current in metal-oxide-semiconductor (MOS) devices. While technology scaling helps to improve the speed and implement more complicated integrated systems, leakage current gets worse and this effect makes the design of ULP systems very challenging.

In this talk, after a short introduction on the conventional methods for implementing ULP digital systems, a new approach for evaluating the performance of this type of circuits will be presented. Following that, a new family of integrated circuits will be introduced which are very convenient for implementing ULP systems.